An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (321, 322) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL1, IL2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (321, 322) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL1) or the two series of yet-to-be-coded bit sequences (IL1, IL2).