A memory system includes a semiconductor memory chip including a substrate, an array of memory cells in arranged each of a plurality of levels in a thickness direction of the substrate, and a plurality of word lines arranged in the thickness direction, each of the word lines being connected to memory cells in one of the levels, and a controller. The controller is configured to determine an offset value with respect to each of a plurality of word line groups that are organized from the plurality of word lines along the thickness direction, and, with respect to each of the word line groups, set a voltage to be applied to the word line group during at least one of write, read, and erase operations, based on a base parameter value and the offset value corresponding to the word line group.