Invention Grant
- Patent Title: CMOS anti-fuse cell
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Application No.: US16143346Application Date: 2018-09-26
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Publication No.: US10395744B2Publication Date: 2019-08-27
- Inventor: Fu-Chang Hsu
- Applicant: NEO Semiconductor, Inc.
- Applicant Address: US CA San Jose
- Assignee: NEO Semiconductor, Inc.
- Current Assignee: NEO Semiconductor, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Intellectual Property Law Group LLP
- Main IPC: G11C17/16
- IPC: G11C17/16 ; H01L23/525 ; H01L27/112 ; G11C17/18 ; H01L27/088 ; H01L27/12

Abstract:
A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N-well and an anti-fuse cell formed on the N-well. The anti-fuse cell includes a drain P+ diffusion deposited in the N-well, a source P+ diffusion deposited in the N-well, and an oxide layer deposited on the N-well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.
Public/Granted literature
- US20190027228A1 CMOS Anti-Fuse Cell Public/Granted day:2019-01-24
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