Invention Grant
- Patent Title: Semiconductor device
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Application No.: US15918309Application Date: 2018-03-12
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Publication No.: US10396549B2Publication Date: 2019-08-27
- Inventor: Masashi Arakawa , Tadashi Fukui , Koji Takayanagi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2014-198264 20140929
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H02H9/04 ; H01L27/02

Abstract:
Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.
Public/Granted literature
- US20180205225A1 SEMICONDUCTOR DEVICE Public/Granted day:2018-07-19
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