Invention Grant
- Patent Title: Failure detection circuit, failure detection system and failure detection method
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Application No.: US15683156Application Date: 2017-08-22
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Publication No.: US10401419B2Publication Date: 2019-09-03
- Inventor: Masafumi Fujimori
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Priority: JP2017-053381 20170317
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H03K5/24 ; H03K19/20

Abstract:
A data failure detection circuit of embodiments includes a monitor signal generation circuit configured to generate a monitor signal to be used to sense failures of a plurality of test mode signals to be respectively input to a plurality of modules, a cascade connection circuit configured to sense a failure of each of the test mode signals and including a plurality of OR circuits, and a comparison circuit configured to compare an output signal from the cascade connection circuit with the monitor signal to determine whether or not a failure exists. In the cascade connection circuit, a plurality of OR circuits are connected in cascade, and the monitor signal is input to one of the OR circuits in a first stage.
Public/Granted literature
- US20180267095A1 FAILURE DETECTION CIRCUIT, FAILURE DETECTION SYSTEM AND FAILURE DETECTION METHOD Public/Granted day:2018-09-20
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