Invention Grant
- Patent Title: Semiconductor integrated circuit and semiconductor integrated circuit diagnosis method
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Application No.: US15691121Application Date: 2017-08-30
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Publication No.: US10401430B2Publication Date: 2019-09-03
- Inventor: Tomoyuki Maekawa
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Priority: JP2017-054930 20170321
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G06F11/267 ; G01R31/3185

Abstract:
A semiconductor device according to an embodiment includes a plurality of scan chains each including a retention flip-flop, and a control section configured to perform restoration of data saved in a retention section of each retention flip-flop by reading the data from the retention section and after the data restoration, perform diagnosis of the retention flip-flops by performing comparison to determine whether or not an expected value of an output data string obtained as a result of a scan shift in the plurality of scan chains before the save and a value of an output data string obtained as a result of a scan shift of data in the plurality of scan chains after the restoration.
Public/Granted literature
- US20180275198A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DIAGNOSIS METHOD Public/Granted day:2018-09-27
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