A signal processing circuit includes a clock generating circuit, a divider circuit, a converter, and an amplifier. The clock generating circuit outputs a first clock. The divider circuit divides the first clock to output a second clock having a frequency lower than a frequency of the first clock. The converter converts an input signal into a digital signal based on a first clock output from the clock generating circuit and a second clock output from the divider circuit. The amplifier, disposed between the clock generating circuit and the divider circuit, has a phase variation property opposite to a phase variation property of the divider circuit. The phase variation property of the divider circuit indicates a relationship between a phase variation amount of an output signal with respect to an input signal in the divider circuit and an ambient temperature of the divider circuit.