- Patent Title: Using a stuttered clock signal to reduce self-induced voltage noise
-
Application No.: US13883265Application Date: 2011-10-31
-
Publication No.: US10401900B2Publication Date: 2019-09-03
- Inventor: Brian S. Leibowitz , Jared L. Zerbe
- Applicant: Brian S. Leibowitz , Jared L. Zerbe
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Lance Kreisman Peninsula Patent Group
- International Application: PCT/US2011/058525 WO 20111031
- International Announcement: WO2012/064537 WO 20120518
- Main IPC: G06F1/08
- IPC: G06F1/08 ; G06F1/12 ; G06F1/3237

Abstract:
The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.
Public/Granted literature
- US20130227329A1 USING A STUTTERED CLOCK SIGNAL TO REDUCE SELF-INDUCED VOLTAGE NOISE Public/Granted day:2013-08-29
Information query