Using a stuttered clock signal to reduce self-induced voltage noise
Abstract:
The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.
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