A pipe latch circuit includes: a pipe latch control block suitable for controlling a plurality of pipe input signals and a plurality of pipe output signals to be activated sequentially or be divided into at least two groups and be activated sequentially by group, depending on a latency setting value, and outputting at least one pipe input signal and at least one pipe output signal; and a pipe latch block coupled between an input node and an output node, and suitable for storing data of the input node in response to the pipe input signal and outputting stored data to the output node in response to the pipe output signal.