Invention Grant
- Patent Title: Memory system and control method
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Application No.: US15684826Application Date: 2017-08-23
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Publication No.: US10402350B2Publication Date: 2019-09-03
- Inventor: Shinichi Kanno
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JP2017-036932 20170228
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F13/16 ; G11C5/02 ; G11C16/04 ; G11C16/08

Abstract:
A memory package in which a plurality of stacked non-volatile memory dies is connected to one another through a plurality of vertical vias is used in a memory system. The dies are classified into a plurality of die groups including a first die group that includes a plurality of dies connected to a first channel, and a second die group that includes a plurality of dies connected to a second channel. A data write/read operation on the first die group is performed through the first channel in response to an I/O command designating a first area corresponding to the first die group, and a data write/read operation on the second die group is performed through the second channel in response to an I/O command designating a second area corresponding to the second die group.
Public/Granted literature
- US20180246821A1 MEMORY SYSTEM AND CONTROL METHOD Public/Granted day:2018-08-30
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