Invention Grant
- Patent Title: Region aware clustering
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Application No.: US15692637Application Date: 2017-08-31
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Publication No.: US10402522B1Publication Date: 2019-09-03
- Inventor: Natarajan Viswanathan , Charles Jay Alpert , Thomas Andrew Newton , William Robert Reece
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each clock driver, the CTS tool applies point-based clustering to the clock drivers of the IC design to obtain one or more clusters.
Public/Granted literature
- US2164619A Apparatus for use with coffee brewers Public/Granted day:1939-07-04
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