Invention Grant
- Patent Title: Method, system, and computer program product for implementing placement using row templates for an electronic design
-
Application No.: US15396156Application Date: 2016-12-30
-
Publication No.: US10402530B1Publication Date: 2019-09-03
- Inventor: Karun Sharma , Yu Liu , Subhashis Mandal , Kanaka Raju Gorle , Jeff Taraldson
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Disclosed are techniques for implementing placement using row templates for an electronic design using row templates. These techniques identify or create a row region in a layout of an electronic design. A row template is applied to the row region to create one or more placement rows in the row region. One or more layout circuit components may then be placed into one or more rows or at one or more locations to create a legal placement layout by guiding placement of the one or more layout circuit components with the row template.
Information query
