Invention Grant
- Patent Title: Semiconductor integrated circuit and semiconductor device
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Application No.: US15910565Application Date: 2018-03-02
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Publication No.: US10403341B2Publication Date: 2019-09-03
- Inventor: Nobuhiro Tsuji , Hiroki Ohkouchi , Shota Note , Masashi Nakata , Yohei Yasuda
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Priority: JP2017-176133 20170913
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/22 ; H03K5/156 ; H03L7/08 ; G06F13/16

Abstract:
A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.
Public/Granted literature
- US20190080734A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE Public/Granted day:2019-03-14
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