- Patent Title: Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
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Application No.: US15628589Application Date: 2017-06-20
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Publication No.: US10403384B2Publication Date: 2019-09-03
- Inventor: Darryl G. Walker
- Applicant: Darryl G. Walker
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C29/12 ; G11C7/22 ; H01L29/78 ; G11C7/04 ; G11C11/419 ; G11C29/02 ; G11C29/14 ; G11C29/16 ; G11C29/46 ; G11C29/48 ; G11C29/50 ; G11C7/06 ; G11C7/10 ; G11C7/12 ; G11C7/14 ; G11C8/08 ; G11C29/04
Abstract:
A method of operating a semiconductor device that has a normal mode of operation and a test mode of operation, can include: generating at least one assist signal in the normal mode of operation wherein, when the at least one assist signal has a first assist logic level, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell as compared to operations without the assist signal, and inhibiting the generation of the at least one assist signal in the test mode of operation, the at least one assist signal has a second assist logic level when inhibited from being generated.
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