Invention Grant
- Patent Title: Multilayer pillar for reduced stress interconnect and method of making same
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Application No.: US15445058Application Date: 2017-02-28
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Publication No.: US10403590B2Publication Date: 2019-09-03
- Inventor: Virendra R. Jadhav , Krystyna W. Semkow , Kamalesh K. Srivastava , Brian R. Sundlof
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran Cole & Calderon, P.C.
- Agent Steven J. Meyers; Andrew M. Calderon
- Main IPC: H01L23/00
- IPC: H01L23/00
Abstract:
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
Public/Granted literature
- US20170170135A1 MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME Public/Granted day:2017-06-15
Information query
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