Invention Grant
- Patent Title: Semiconductor device
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Application No.: US16075009Application Date: 2017-01-12
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Publication No.: US10403620B2Publication Date: 2019-09-03
- Inventor: Shinichirou Wada , Katsumi Ikegaya
- Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
- Applicant Address: JP Hitachinaka-Shi
- Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
- Current Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
- Current Assignee Address: JP Hitachinaka-Shi
- Agency: Foley & Lardner LLP
- Priority: JP2016-032697 20160224
- International Application: PCT/JP2017/000701 WO 20170112
- International Announcement: WO2017/145542 WO 20170831
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/12 ; H01L27/088 ; H01L21/762 ; H03K17/082 ; H01L29/739

Abstract:
To provide a semiconductor device capable of restricting the substrate bias effect of a high-side transistor while enhancing the heat radiation property of a low-side transistor.A high-side NMOS transistor 101 is formed in a region S1 on the surface of a SOI substrate 30. A trench 41 surrounds the high-side NMOS transistor 101. SiO2 (first insulator) embeds the trench 41. A low-side NMOS transistor 102 is formed in a region S2 on the surface of the SOI substrate 30 around the trench 41. The side face Sf connecting the region S2 forming the low-side NMOS transistor 102 therein and the backside of the SOI substrate 30 is exposed.
Public/Granted literature
- US20190043851A1 SEMICONDUCTOR DEVICE Public/Granted day:2019-02-07
Information query
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