Invention Grant
- Patent Title: 3D-capacitor structure
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Application No.: US16149353Application Date: 2018-10-02
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Publication No.: US10403710B2Publication Date: 2019-09-03
- Inventor: Frédéric Voiron , Jean-René Tenailleau
- Applicant: Murata Integrated Passive Solutions
- Applicant Address: FR Caen
- Assignee: Murata Integrated Passive Solutions
- Current Assignee: Murata Integrated Passive Solutions
- Current Assignee Address: FR Caen
- Agency: Arent Fox LLP
- Priority: EP16306200 20160920
- Main IPC: H01L29/94
- IPC: H01L29/94 ; H01L49/02 ; H01L27/08 ; H01L29/06 ; H01G11/26

Abstract:
A 3D-capacitor structure that is based on a trench network etched from a top face of a substrate to form an array of separated pillars. The 3D-capacitor structure includes a double capacitor layer stack that extends continuously on top faces of the pillars at the substrate top face, on trench sidewalls and also on a trench bottom. The trench network is modified locally for contacting a second electrode of the double capacitor layer stack while ensuring that no unwanted short-circuit may occur between the second electrode and a third electrode of the double capacitor layer stack. The 3D-capacitor structure provides an improved trade-off between high capacitor density and certainty of no unwanted short-circuit.
Public/Granted literature
- US20190035880A1 3D-CAPACITOR STRUCTURE Public/Granted day:2019-01-31
Information query
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