Invention Grant
- Patent Title: MOS-based power semiconductor device having increased current carrying area and method of fabricating same
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Application No.: US16006571Application Date: 2018-06-12
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Publication No.: US10403720B2Publication Date: 2019-09-03
- Inventor: James A. Cooper
- Applicant: Purdue Research Foundation
- Applicant Address: US IN West Lafayette
- Assignee: Purdue Research Foundation
- Current Assignee: Purdue Research Foundation
- Current Assignee Address: US IN West Lafayette
- Agency: Maginot, Moore & Beck LLP
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/06 ; H01L29/10 ; H01L29/16 ; H01L29/49 ; H01L29/66 ; H01L29/78 ; H01L29/739

Abstract:
A semiconductor device fabrication method includes forming first and second spaced apart base regions and source regions in a substrate with a portion of a drift region therebetween. The method further includes forming at least a first trench extending laterally through the base region, the drift region and the source region, the first trench extending vertically partially through the source region. The method also includes forming a first oxide layer over the trenched upper surface, and forming a polysilicon layer over the first oxide layer. The polysilicon layer is patterned to form the gate conductor, and a drain contact is formed on a bottom surface of the semiconductor substrate.
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