Invention Grant
- Patent Title: Logic circuitry using three dimensionally stacked dual-gate thin-film transistors
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Application No.: US15907444Application Date: 2018-02-28
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Publication No.: US10403759B2Publication Date: 2019-09-03
- Inventor: Sungjune Jung , Jimin Kwon
- Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION
- Applicant Address: KR Pohang-si
- Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
- Current Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
- Current Assignee Address: KR Pohang-si
- Agency: Lex IP Meister, PLLC
- Priority: KR10-2017-0027005 20170302
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L51/05 ; H01L27/28 ; H01L51/00 ; H03K19/0948 ; H03K19/20 ; H03K19/21 ; H01L27/12 ; H01L27/06

Abstract:
Disclosed is a logic circuit using three-dimensionally stacked dual-gate thin-film transistors, including a substrate, a first dual-gate thin-film transistor on the substrate, a second dual-gate thin-film transistor on the first dual-gate thin-film transistor, and a third dual-gate thin-film transistor on the second dual-gate thin-film transistor, wherein the first dual-gate thin-film transistor, the second dual-gate thin-film transistor and the third dual-gate thin-film transistor are electrically connected to each other. The logic circuit of the invention is configured such that dual-gate thin-film transistors are three-dimensionally stacked, whereby the advantages of the dual-gate structure and of thin-film transistors can be exhibited together and the degree of integration can be drastically increased, and a logic gate is made in the area of a single transistor, thereby remarkably simplifying wire and circuit designs.
Public/Granted literature
- US20180254351A1 LOGIC CIRCUITRY USING THREE DIMENSIONALLY STACKED DUAL-GATE THIN-FILM TRANSISTORS Public/Granted day:2018-09-06
Information query
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