Invention Grant
- Patent Title: Low BER hard-decision LDPC decoder
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Application No.: US16137947Application Date: 2018-09-21
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Publication No.: US10404279B2Publication Date: 2019-09-03
- Inventor: Paul Edward Hanham , David Malcolm Symons , Neil Buxton
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/11 ; G06F11/10 ; H03M13/29 ; H03M13/37 ; H03M13/15 ; G11C29/04

Abstract:
A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.
Public/Granted literature
- US20190103882A1 LOW BER HARD-DECISION LDPC DECODER Public/Granted day:2019-04-04
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