Invention Grant
- Patent Title: Terminal device and integrated circuit
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Application No.: US15317029Application Date: 2015-05-29
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Publication No.: US10404428B2Publication Date: 2019-09-03
- Inventor: Ryota Yamada , Takashi Yoshimoto , Kazuyuki Shimezawa
- Applicant: Sharp Kabushiki Kaisha
- Applicant Address: JP Sakai
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Sakai
- Agency: Keating & Bennett, LLP
- Priority: JP2014-119167 20140610
- International Application: PCT/JP2015/065507 WO 20150529
- International Announcement: WO2015/190313 WO 20151217
- Main IPC: H04L5/00
- IPC: H04L5/00 ; H04J11/00 ; H04W92/10 ; H04W16/06 ; H04W72/04

Abstract:
Interference is mitigated by effective knowledge and/or effective information about an interference signal. A higher layer in which a base station apparatus configures first interference information used for the terminal apparatus to mitigate interference from a cell-specific reference signal and/or second interference information used for the terminal apparatus to mitigate interference at least from a downlink shared channel; and a signal detection unit configured to mitigate the interference from the cell-specific reference signal based on the first interference information and to mitigate the interference at least from the downlink shared channel based on the second interference information.
Public/Granted literature
- US20170099123A1 TERMINAL DEVICE AND INTEGRATED CIRCUIT Public/Granted day:2017-04-06
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