A system includes a real-time computer having a real-time clock programmed to output a clock signal, a binary clock display programmed to display a first amount of time that has elapsed according to the clock signal, a host computer programmed to simulate a virtual environment including a virtual clock display programmed to represent a second amount of time that has elapsed according to the clock signal, and a latency processor programmed to calculate latency of the host computer based on a difference between the first amount of time and the second amount of time.