Invention Grant
- Patent Title: Apparatus and method for efficiently accessing memory when performing a horizontal data reduction
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Application No.: US15922833Application Date: 2018-03-15
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Publication No.: US10409571B1Publication Date: 2019-09-10
- Inventor: Marek Targowski
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F8/41
- IPC: G06F8/41 ; G06F9/48 ; G06F9/52

Abstract:
Apparatus and method for optimizing shader execution. For example, one embodiment of a graphics processing apparatus comprises: a plurality of execution units to execute shader programs; optimization detection circuitry and/or logic to identify one or more portions of shader program code to be optimized including one or more reduction operations which require read/write memory operations and associated barrier operations; and optimization circuitry and/or logic to optimize the shader program code by converting a plurality of the read/write memory operations to read/write register operations and removing one or more barrier operations to generate optimized shader program code; the execution units to execute the optimized shader program code.
Public/Granted literature
- US20190286430A1 APPARATUS AND METHOD FOR EFFICIENTLY ACCESSING MEMORY WHEN PERFORMING A HORIZONTAL DATA REDUCTION Public/Granted day:2019-09-19
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