Invention Grant
- Patent Title: Method and apparatus for modelling power consumption of integrated circuit
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Application No.: US14420303Application Date: 2013-08-08
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Publication No.: US10409936B2Publication Date: 2019-09-10
- Inventor: Jihwan Park
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR10-2012-0086647 20120808
- International Application: PCT/KR2013/007150 WO 20130808
- International Announcement: WO2014/025212 WO 20140213
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F1/3237 ; G06F17/10

Abstract:
A method of modeling power consumption of an integrated circuit and an apparatus for supporting the same are provided. The method of modeling power consumption of an integrated circuit includes: grasping information about a clock gating enable signal of the integrated circuit; determining a modeling level using a change rate of the number of the clock enable signal; and extracting a power state according to the modeling level and the number of the clock gating enable signal and modeling power consumption in the power state. Thereby, because a power state can be defined with only the number of a clock gating enable signal, a dynamic power consumption amount can be quickly and accurately estimated.
Public/Granted literature
- US20150220672A1 METHOD AND APPARATUS FOR MODELLING POWER CONSUMPTION OF INTEGRATED CIRCUIT Public/Granted day:2015-08-06
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