Invention Grant
- Patent Title: FPGA/ASIC framework and method for requirements-based trust assessment
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Application No.: US15446787Application Date: 2017-03-01
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Publication No.: US10409994B1Publication Date: 2019-09-10
- Inventor: Vivian G. Kammler , Robert C. Armstrong , Andrew Michael Smith , Jackson R. Mayo
- Applicant: National Technology & Engineering Solutions of Sandia, LLC
- Applicant Address: US NM Albuquerque
- Assignee: National Technology & Engineering Solutions of Sandia, LLC
- Current Assignee: National Technology & Engineering Solutions of Sandia, LLC
- Current Assignee Address: US NM Albuquerque
- Agency: Medley, Behrens & Lewis, LLC
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F12/14 ; G06F12/16 ; G08B23/00 ; G06F21/57 ; G06F17/50 ; G06F21/76

Abstract:
Described herein are various technologies for metrics-based assessment and trust verification of netlists for hardware logic devices (e.g., ASICs, FPGAs, etc.). A computing system translates a netlist of a hardware logic device into a Boolean network. The computing system generates and assigns metrics to edges of the Boolean network. The metrics comprise a coverage metric, a rare trigger metric, and an influence metric. Based upon the metrics, the computing system assigns the nodes in the Boolean network criticality values. The computing system determines a likelihood of a vulnerability in the netlist based upon the criticality values. The computing can output an indication as to whether the netlist is trusted based upon the determined likelihood of a vulnerability in the netlist.
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