Gate driving circuit
Abstract:
A gate driving circuit including an input terminal, N delay units, a control signal bus, N buffer units and N output pads is disclosed. The input terminal receives a timing control signal including a total delay time. The N delay units are connected to the input terminal in order. Delay times of N delay units are adjustable and a sum of them is the total delay time. The control signal bus determines delay times of N delay units respectively according to the timing control signal. A first buffer unit of N buffer units is coupled between the input terminal and a first delay unit of N delay units; a second buffer unit, a third buffer unit . . . and an N-th buffer unit are coupled between two corresponding delay units respectively. The N output pads, correspondingly coupled to the N buffer units, output N gate driving signals respectively.
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