Invention Grant
- Patent Title: Semiconductor integrated circuit adapted to output pass/fail results of internal operations
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Application No.: US15831805Application Date: 2017-12-05
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Publication No.: US10410731B2Publication Date: 2019-09-10
- Inventor: Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2001-386596 20011219; JP2002-311475 20021025
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C16/34 ; G11C7/06 ; G11C7/10 ; G11C16/10 ; G11C16/26 ; G06F3/06 ; G06F12/02 ; G11C16/06 ; G11C16/08
Abstract:
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
Public/Granted literature
- US20180096729A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS Public/Granted day:2018-04-05
Information query
