- Patent Title: Semiconductor device including a superlattice as a gettering layer
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Application No.: US15980893Application Date: 2018-05-16
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Publication No.: US10410880B2Publication Date: 2019-09-10
- Inventor: Hideki Takeuchi
- Applicant: Atomera Incorporated
- Applicant Address: US CA Los Gatos
- Assignee: ATOMERA INCORPORATED
- Current Assignee: ATOMERA INCORPORATED
- Current Assignee Address: US CA Los Gatos
- Agency: Allen, Dyer, Doppelt + Gilchrist, P.A.
- Main IPC: H01L21/322
- IPC: H01L21/322 ; H01L21/02 ; H01L23/522 ; H01L21/768 ; H01L23/48 ; H01L29/15

Abstract:
A semiconductor device may include a semiconductor substrate having a front side and a back side opposite the front side, and a superlattice gettering layer on the front side of a semiconductor substrate. The superlattice gettering layer may include stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The device may further include an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, at least one semiconductor circuit in the active semiconductor layer, at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer to the back side of the semiconductor substrate. The superlattice gettering layer may further include gettered metal ions.
Public/Granted literature
- US20180337063A1 SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AS A GETTERING LAYER Public/Granted day:2018-11-22
Information query
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