Invention Grant
- Patent Title: Fabricating method of nanosheet transistor spacer including inner spacer
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Application No.: US15837613Application Date: 2017-12-11
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Publication No.: US10410931B2Publication Date: 2019-09-10
- Inventor: Myung Gil Kang , Hyun Seung Song , Sang Woo Lee
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/66 ; H01L29/06 ; H01L21/265 ; H01L21/306 ; H01L21/8234 ; H01L21/02 ; H01L29/775 ; B82Y10/00 ; H01L29/423

Abstract:
A fabricating method of a nanosheet transistor includes: forming a plurality of sacrificial layers and a plurality of channel layers on a substrate, wherein the sacrificial layers and the channel layers are alternately arranged; forming a plurality of gates on an uppermost channel layer, wherein the gates are spaced apart from each other; forming a mask on each of the gates; selectively etching the sacrificial layers between the gates, wherein the sacrificial layers between the gates are removed by the etching; depositing a spacer material along sidewalls of the gates and in areas from which the sacrificial layers have been removed; and etching the spacer material to form sidewall spacers along the sidewalls of the gates and inner spacers between the channel layers.
Public/Granted literature
- US20180197794A1 FABRICATING METHOD OF NANOSHEET TRANSISTOR SPACER INCLUDING INNER SPACER Public/Granted day:2018-07-12
Information query
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