Invention Grant
- Patent Title: Lead package and method for minimizing deflection in microelectronic packaging
-
Application No.: US16015631Application Date: 2018-06-22
-
Publication No.: US10410959B2Publication Date: 2019-09-10
- Inventor: Franklin Kim , Mark Eblen , Shinichi Hira
- Applicant: Kyocera International, Inc.
- Applicant Address: US CA San Diego
- Assignee: Kyocera International, Inc.
- Current Assignee: Kyocera International, Inc.
- Current Assignee Address: US CA San Diego
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/367 ; H01L21/48 ; H01L23/08 ; H01L23/04 ; H01L23/538 ; H01L23/36

Abstract:
Package deflection and mechanical stress of microelectronic packaging is minimized in a two step manufacturing process. In a first step, a ceramic insulator is high-temperature bonded between a wraparound lead layer and a buffer layer of a same material as the lead layer to provide a symmetrically balanced three-layer structure. In a second step, the three-layer structure is high temperature bonded, using a lower melt point braze, to a heat spreader. This package configuration minimizes package deflection, and thereby improves thermal dissipation and reliability of the package.
Public/Granted literature
- US20180374781A1 LEAD PACKAGE AND METHOD FOR MINIMIZING DEFLECTION IN MICROELECTRONIC PACKAGING Public/Granted day:2018-12-27
Information query
IPC分类: