Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
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Application No.: US15900664Application Date: 2018-02-20
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Publication No.: US10411025B2Publication Date: 2019-09-10
- Inventor: Yoshihisa Matsubara
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2017-082021 20170418
- Main IPC: H01L27/11546
- IPC: H01L27/11546 ; H01L29/788 ; H01L29/423 ; H01L29/66 ; H01L21/265 ; H01L21/28 ; H01L29/792 ; H01L27/1157 ; H01L27/11573
Abstract:
In a semiconductor device including a higher-breakdown-voltage MISFET, an improvement is achieved in the breakdown voltage of the MISFET, while preventing an increase in the area of the MISFET. A gate pattern including a gate electrode of the higher-breakdown-voltage MISFET is formed higher in level than a gate pattern including a gate electrode of a lower-breakdown-voltage MISFET. An n+-type semiconductor region included in each of source/drain regions of the higher-breakdown-voltage MISFET is formed deeper than an n+-type semiconductor region included in each of source/drain regions of the lower-breakdown-voltage MISFET.
Public/Granted literature
- US20180301462A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2018-10-18
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