Invention Grant
- Patent Title: Integrated computing structures formed on silicon
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Application No.: US15641558Application Date: 2017-07-05
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Publication No.: US10411026B2Publication Date: 2019-09-10
- Inventor: Arup Bhattacharyya
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H01L27/11568
- IPC: H01L27/11568 ; H01L21/28 ; H01L21/762 ; H01L21/8238 ; H01L21/285 ; H01L27/092 ; H01L29/06 ; H01L29/08 ; H01L29/45 ; H01L23/535 ; H01L29/423 ; H01L27/11573

Abstract:
The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions.
Public/Granted literature
- US20190013323A1 INTEGRATED COMPUTING STRUCTURES FORMED ON SILICON Public/Granted day:2019-01-10
Information query
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