Invention Grant
- Patent Title: Semiconductor memory device including a selection element pattern confined to a hole
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Application No.: US16019346Application Date: 2018-06-26
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Publication No.: US10411070B2Publication Date: 2019-09-10
- Inventor: Jong Chul Lee
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon
- Assignee: SK HYNIX INC.
- Current Assignee: SK HYNIX INC.
- Current Assignee Address: KR Icheon
- Priority: KR10-2017-0156377 20171122
- Main IPC: G06F12/00
- IPC: G06F12/00 ; H01L27/24 ; H01L45/00 ; G06F3/06

Abstract:
An electronic device having a semiconductor memory device is provided. The semiconductor memory device may include a lower interlayer insulating layer having a hole; an upper interlayer insulating layer disposed on the lower interlayer insulating layer; and a memory cell stack including a lower element and an upper element, the lower element being confined to the hole of the lower interlayer insulating layer, the upper element being surrounded by the upper interlayer insulating layer. The lower element may include a lower electrode and a selection element pattern disposed on the lower electrode. The upper element may include a memory pattern disposed on the selection element pattern and an upper electrode disposed on the memory pattern.
Public/Granted literature
- US20190157346A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING A SELECTION ELEMENT PATTERN CONFINED TO A HOLE Public/Granted day:2019-05-23
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