Invention Grant
- Patent Title: Cascode connected SiC-JFET with SiC-SBD and enhancement device
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Application No.: US16102516Application Date: 2018-08-13
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Publication No.: US10411698B2Publication Date: 2019-09-10
- Inventor: Tetsuo Sato , Koichi Yamazaki
- Applicant: RENESAS ELECTRONICS AMERICA INC.
- Applicant Address: US CA Santa Clara
- Assignee: RENESAS ELECTRONICS AMERICA INC.
- Current Assignee: RENESAS ELECTRONICS AMERICA INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Foley & Lardner LLP
- Main IPC: H02M3/155
- IPC: H02M3/155 ; H03K17/687 ; H03K17/567 ; H03K17/74 ; H03K17/0416 ; H02M7/00

Abstract:
An apparatus that includes a first device connected to an inductor. The first device includes a first silicon carbide (SiC) junction gate field-effect transistor (JFET), a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET, and a first silicon (Si) transistor connected to transmit current to a source of the first SiC JFET. An inductor input terminal is connected to the drain of the first SiC JFET.
Public/Granted literature
- US20180351548A1 CASCODE CONNECTED SIC-JFET WITH SIC-SBD AND ENHANCEMENT DEVICE Public/Granted day:2018-12-06
Information query
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