Invention Grant
- Patent Title: Phase-locked loop output adjustment
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Application No.: US15714372Application Date: 2017-09-25
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Publication No.: US10411718B2Publication Date: 2019-09-10
- Inventor: Karthik Nagarajan , Chenling Huang , Debesh Bhatta
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Paradice and Li LLP/Qualcomm
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/093 ; H03L7/089 ; H03K5/26 ; H03K5/1252 ; H03L7/07 ; H03L7/087 ; H03L7/22 ; H03L7/23 ; H03K5/00

Abstract:
A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.
Public/Granted literature
- US20190097640A1 PHASE-LOCKED LOOP OUTPUT ADJUSTMENT Public/Granted day:2019-03-28
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