Invention Grant
- Patent Title: On-chip test circuit for magnetic random access memory (MRAM)
-
Application No.: US14749324Application Date: 2015-06-24
-
Publication No.: US10416217B2Publication Date: 2019-09-17
- Inventor: Sasikanth Manipatruni , Chia-Ching Lin , Yih Wang , Ian A. Young
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G01R31/12
- IPC: G01R31/12 ; G01R29/26 ; G11C11/16 ; G11C29/50 ; G01R31/28

Abstract:
Embodiments include a test circuit to test one or more magnetic tunnel junctions (MTJs) of a magnetic random access memory (MRAM). The test circuit may measure a 1/f noise of the MTJ in the time domain, and determine a power spectral density (PSD) of the 1/f noise. The test circuit may estimate one or more parameters of the MTJ and/or MRAM based on the PSD. For example, the test circuit may determine a noise parameter, such as a Hooge alpha parameter, based on the PSD, and may estimate the one or more parameters of the MTJ and/or MRAM based on the 1/f parameter. Other embodiments may be described and claimed.
Public/Granted literature
- US20160377669A1 ON-CHIP TEST CIRCUIT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) Public/Granted day:2016-12-29
Information query