Invention Grant
- Patent Title: Wafer inspection method and wafer inspection device
-
Application No.: US15763312Application Date: 2016-07-11
-
Publication No.: US10416229B2Publication Date: 2019-09-17
- Inventor: Hiroshi Yamada
- Applicant: TOKYO ELECTRON LIMITED
- Applicant Address: JP Tokyo
- Assignee: TOKYO ELECTRON LIMITED
- Current Assignee: TOKYO ELECTRON LIMITED
- Current Assignee Address: JP Tokyo
- Agency: Nath, Goldberg & Meyer
- Agent Jerald L. Meyer
- Priority: JP2015-194390 20150930
- International Application: PCT/JP2016/070923 WO 20160711
- International Announcement: WO2017/056643 WO 20170406
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G01R31/28 ; H01L21/68
Abstract:
Provided is a wafer inspection method wherein a chuck top can be properly received. When an aligner receives a chuck top after a wafer W has been inspected, the distance between the chuck top and a chuck base is adjusted by adjusting the inclination of the chuck base such that the chuck top height, which is the distance between the chuck top and the chuck base after the chuck top is held, is a height in which any of 0 to 200 μm is added to the chuck top height before the chuck top is held.
Public/Granted literature
- US20180275192A1 Wafer Inspection Method and Wafer Inspection Device Public/Granted day:2018-09-27
Information query
