Invention Grant
- Patent Title: Semiconductor device
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Application No.: US16176327Application Date: 2018-10-31
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Publication No.: US10416382B2Publication Date: 2019-09-17
- Inventor: Yasutaka Nakashiba , Shinichi Watanuki
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2017-244282 20171220
- Main IPC: G02B6/10
- IPC: G02B6/10 ; G02B6/122 ; G02B6/12

Abstract:
In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.
Public/Granted literature
- US20190187370A1 SEMICONDUCTOR DEVICE Public/Granted day:2019-06-20
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