A semiconductor memory device includes a memory cell array including a plurality of memory cells connected to a plurality of bit lines, a control signal generating circuit configured to generate a first control signal in response to a first operating temperature of the semiconductor memory device and a second control signal in response to a second operating temperature of the semiconductor memory device, a precharge circuit configured to provide a precharge current to a first bit line of the plurality of bit lines in response to an enable signal, and a boost circuit configured to provide a boost current to the first bit line in response to the enable signal, wherein the magnitude of the boost circuit is responsive to one of the first and second control signals.