Invention Grant
- Patent Title: Method for controlling memory device
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Application No.: US15907286Application Date: 2018-02-27
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Publication No.: US10418107B2Publication Date: 2019-09-17
- Inventor: Yoichi Minemura
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JP2017-056416 20170322
- Main IPC: G11C16/10
- IPC: G11C16/10 ; H01L23/528 ; H01L29/10 ; H01L27/11568 ; G11C16/04 ; G11C16/34 ; H01L29/08 ; G11C16/08 ; G11C16/12 ; H01L27/11565 ; H01L27/11582

Abstract:
A memory device includes stacked word lines stacked and a semiconductor channel passing through the word lines in a first direction. Memory cells are disposed along the semiconductor channel in the first direction. Each memory cell includes a charge retention film between the semiconductor channel and a respective word line in the plurality of word lines. A controller is connected to the semiconductor channel and the word lines and configured to apply a program voltage during a program operation to a memory cell at a potential that increases in voltage steps, and a voltage increment between the voltage steps decreases during the program operation. The increment voltage is changed by the controller depending on a position of the memory cell along the semiconductor channel in the first direction.
Public/Granted literature
- US20180277221A1 METHOD FOR CONTROLLING MEMORY DEVICE Public/Granted day:2018-09-27
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