Invention Grant
- Patent Title: Method of forming vias using silicon on insulator substrate
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Application No.: US15472184Application Date: 2017-03-28
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Publication No.: US10418311B2Publication Date: 2019-09-17
- Inventor: Toshiyuki Maenosono , Yuta Kikuchi , Manabu Ito , Yoshihiro Saeki
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/768 ; H01L23/498 ; H01L23/538
Abstract:
Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.
Public/Granted literature
- US20180286795A1 METHOD OF FORMING VIAS USING SILICON ON INSULATOR SUBSTRATE Public/Granted day:2018-10-04
Information query
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