Invention Grant
- Patent Title: Stacked semiconductor package having mold vias and method for manufacturing the same
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Application No.: US15715449Application Date: 2017-09-26
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Publication No.: US10418353B2Publication Date: 2019-09-17
- Inventor: Sang-Eun Lee , Hyung-Dong Lee , Eun Ko
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2017-0058458 20170511
- Main IPC: H01L25/18
- IPC: H01L25/18 ; H01L23/31 ; H01L25/065 ; H01L23/00 ; H01L23/48 ; H01L23/538 ; H01L21/56 ; H01L25/00 ; H01L21/78 ; H01L23/498 ; H01L21/768

Abstract:
A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.
Public/Granted literature
- US20180331087A1 STACKED SEMICONDUCTOR PACKAGE HAVING MOLD VIAS AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2018-11-15
Information query
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