A method of operating a semiconductor memory device including a memory cell array and an error correction circuit is provided as follows. A write command, main data and an address are received from a memory controller. An error correction data unit is provided to the error correction circuit. The error correction data unit includes the main data. At least one parity bit is generated based on the error correction data unit. A write operation is performed, in response to the write command, on a target page selected by the address so that the at least one parity bit and the main data are written to the target page and the at least one parity data is written later than the main data to the target page.