Invention Grant
- Patent Title: Hierarchical depth buffer back annotaton
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Application No.: US15477049Application Date: 2017-04-01
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Publication No.: US10424107B2Publication Date: 2019-09-24
- Inventor: Vasanth Ranganathan , Saikat Mandal , Saurabh Sharma , Vamsee Vardhan Chivukula , Karol A. Szerszen , Aleksander Olek Neyman , Altug Koker , Prasoonkumar Surti , Abhishek Appu , Joydeep Ray , Art Hunter , Luis F. Cruz Camacho , Akshay R. Chada
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Spectrum IP Law Group LLC
- Main IPC: G06T15/00
- IPC: G06T15/00 ; G06T15/40

Abstract:
Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.
Public/Granted literature
- US20180286113A1 HIERARCHICAL DEPTH BUFFER BACK ANNOTATON Public/Granted day:2018-10-04
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |