A semiconductor memory device includes memory cells connected to word lines and bit lines. In a verification operation, a controller applies first and second verification voltages to a word line in sequence, a first voltage to a first bit line of a first cell and a second voltage to second bit line during first level verification, and, if the first cell passes first voltage level verification, the first voltage is then applied to both the first and second bit lines while the second verification voltage is applied to the word line.