- Patent Title: Erasing method for flash memory using a memory management apparatus
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Application No.: US15902325Application Date: 2018-02-22
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Publication No.: US10424386B2Publication Date: 2019-09-24
- Inventor: Chih-Hao Chen
- Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
- Applicant Address: TW Hsinchu
- Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
- Current Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
- Current Assignee Address: TW Hsinchu
- Agency: Marquez IP Law Office, PLLC
- Agent Juan Carlos A. Marquez
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C11/56 ; G11C16/14

Abstract:
An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address that has the under-erased transistor memory cell.
Public/Granted literature
- US20190259461A1 ERASING METHOD USED IN FLASH MEMORY Public/Granted day:2019-08-22
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