- Patent Title: Method of integrating a charge-trapping gate stack into a CMOS flow
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Application No.: US16043411Application Date: 2018-07-24
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Publication No.: US10424592B2Publication Date: 2019-09-24
- Inventor: Krishnaswamy Ramkumar
- Applicant: Longitude Flash Memory Solutions Ltd.
- Applicant Address: IE Dublin
- Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Current Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Current Assignee Address: IE Dublin
- Agency: Kunzler Bean & Adamson
- Main IPC: H01L27/11573
- IPC: H01L27/11573 ; H01L21/28 ; H01L27/11565 ; H01L27/11568 ; H01L29/49 ; H01L29/792 ; H01L21/8234

Abstract:
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
Public/Granted literature
- US20190067313A1 METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW Public/Granted day:2019-02-28
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