Invention Grant
- Patent Title: Transistors having gates with a lift-up region
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Application No.: US15788216Application Date: 2017-10-19
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Publication No.: US10424647B2Publication Date: 2019-09-24
- Inventor: Jun Cai
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/40 ; H01L29/78 ; H01L29/10 ; H01L21/265 ; H01L29/66 ; H01L21/02 ; H01L29/06 ; H01L29/423

Abstract:
In accordance with at least one embodiment of the invention, a transistor comprises a semiconductor, a first drift layer, a drain region, a body region, a source region, a shallow trench isolation region, a dielectric, and a gate. The first drift layer is formed in the semiconductor and has majority carriers of a first type. The drain region is formed in the first drift layer and has majority carriers of the first type. The body region is formed in the semiconductor and has majority carriers of a second type. The source region is formed in the body region and has majority carriers of the first type. The shallow trench isolation region is formed in the first drift layer and disposed between the drain region and the body region. The dielectric is formed on the semiconductor, and the gate is formed over the dielectric and has a lift-up region.
Public/Granted literature
- US20190123155A1 TRANSISTORS HAVING GATES WITH A LIFT-UP REGION Public/Granted day:2019-04-25
Information query
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