Invention Grant
- Patent Title: Dual gate LDMOS and a process of forming thereof
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Application No.: US15842899Application Date: 2017-12-15
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Publication No.: US10424655B2Publication Date: 2019-09-24
- Inventor: Ming Li , Jeoung Mo Koo , Raj Verma Purakh
- Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Thompson Hine LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/10 ; H01L29/423 ; H01L29/49 ; H01L29/08 ; H01L21/265 ; H01L21/02 ; H01L29/78 ; H01L29/06 ; H01L21/28 ; H01L29/36 ; H01L21/762 ; H01L21/66 ; H01L29/40 ; H01L27/092 ; H01L21/3105 ; H01L21/266 ; H01L21/3213
Abstract:
A method for forming a high voltage device is disclosed. The method comprises providing a substrate defined with a high voltage device region. A device well is formed to encompass the high voltage device region. A drift region is formed within the device well. A body well is formed within the device well adjacent to the drift region. A variable thickness gate dielectric is formed on the substrate. Forming the variable thickness gate dielectric comprises patterned a sacrificial polysilicon layer and oxidizing the patterned sacrificial polysilicon layer to define a thick gate oxide having sloped sidewalls. A gate electrode is formed on the variable thickness gate dielectric, wherein the gate electrode partially overlaps the thick gate oxide. A first and a second source/drain (S/D) region is formed adjacent to first and second sides of the variable thickness gate dielectric.
Public/Granted literature
- US20190189779A1 DUAL GATE LDMOS AND A PROCESS OF FORMING THEREOF Public/Granted day:2019-06-20
Information query
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