Invention Grant
- Patent Title: Leadframe and integrated circuit connection arrangement
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Application No.: US15680034Application Date: 2017-08-17
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Publication No.: US10424666B2Publication Date: 2019-09-24
- Inventor: Shanghui Larry Tu , Michael A. Stuber , Befruz Tasbas , Stuart B. Molin , Raymond Jiang
- Applicant: Silanna Asia Pte Ltd
- Applicant Address: SG Singapore
- Assignee: Silanna Asia Pte Ltd
- Current Assignee: Silanna Asia Pte Ltd
- Current Assignee Address: SG Singapore
- Agency: MLO, a professional corp.
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/10 ; H01L27/12 ; H01L29/78 ; H01L29/06 ; H01L21/84 ; H01L21/74 ; H01L29/66 ; H01L21/48 ; H01L21/768 ; H01L23/48 ; H01L23/495 ; H01L23/00 ; H01L29/417 ; H01L23/522 ; H01L23/535 ; H01L25/00 ; H01L23/485
Abstract:
A semiconductor package includes a leadframe having perimeter package leads and electrical connectors, a single semiconductor die having a back-side electrical contact and front-side electrical contacts, an electrically conductive clip (“clip”), and a top semiconductor die having a frontside and a backside. The single semiconductor die includes two or more transistors. Two or more of the front-side electrical contacts of the semiconductor die are electrically coupled to and physically mounted to respective electrical contacts of the leadframe. An electrical contact surface of the clip is electrically coupled to and physically mounted to an electrical connector of the leadframe. Another electrical contact surface of the clip is physically mounted to and electrically coupled to the back-side electrical contact of the semiconductor die. The backside of the top semiconductor die is physically mounted to yet another surface of the electrically conductive clip.
Public/Granted literature
- US20180240740A1 LEADFRAME AND INTEGRATED CIRCUIT CONNECTION ARRANGEMENT Public/Granted day:2018-08-23
Information query
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